Editorial composite of server hardware and computer memory; representative photographs by panumas nikhomkhai and Sergei Starostin/Pexels, cropped and combined by MBN.

Positron wins new backing for an AI chip built around cheaper memory

Written by Joseph Nordqvist

Published: 17:30, September 13, 2026

Liberty Global’s technology investment arm has joined Positron AI’s latest financing, backing a chip company that wants to reduce the cost of running artificial intelligence models by changing how its next generation of hardware uses memory.

Liberty Global Tech Ventures announced its participation on September 11. It did not disclose its individual investment. Positron had announced a financing package of up to $875 million a day earlier, with a stated $5 billion post-money valuation, the value assigned to the business after the financing.

The company’s announcement describes two stages: a $375 million Series C round at a $3.5 billion pre-money valuation, followed by a Series C-1 of up to $500 million. That wording does not establish that the entire maximum amount has already arrived as cash.

From training AI to answering customers

Positron concentrates on inference, the process of using a trained AI model to produce an answer, recommendation or other output. Training builds the model; inference is the repeated work involved in serving its users.

For a company selling an AI service, the cost of those repeated requests affects what it can charge and the margin it can retain. Hardware also has to respond quickly enough for customers while fitting the power and cooling available in a data center.

Liberty Global’s announcement identifies Oracle, Jump Trading and Parasail among Positron’s customers. Positron says it is deploying more than 50 racks of its existing Atlas systems at Oracle Cloud Infrastructure, with Parasail using that capacity for its inference service.

The new design changes the memory equation

Positron’s planned Asimov chip uses LPDDR5X, a type of low-power memory, in place of high-bandwidth memory, or HBM. HBM stacks memory chips to move large amounts of data quickly and is a major component of many AI accelerators.

The company says its Asimov architecture is designed to use memory capacity and bandwidth efficiently without relying on the same HBM supply chain. Bandwidth measures how quickly data can move; capacity measures how much can be stored. Both can constrain a system even when its processor can perform calculations very quickly.

Those are design and commercial claims for a forthcoming product. They do not establish how Asimov will perform across customers’ workloads once production systems are available.

The memory change also applies to the next generation. The published Atlas specifications list eight accelerators with 32 gigabytes of HBM each. Describing all Positron products as avoiding HBM would therefore be inaccurate.

Production is still ahead

Asimov is scheduled to reach tapeout at the end of 2026. Tapeout is the point when a chip design is sent for manufacturing; it is followed by fabrication, testing and preparation for volume production.

The company and Liberty Global put production in the second half of 2027. Asimov is intended to power Titan, Positron’s next-generation inference system. The financing will support the chip development and the work needed to bring those systems to market.

Memory is one of several places where companies are trying to lower AI infrastructure costs. Our recent report on Ayar Labs’ optical connections for AI chips examined another: moving data between components using light.

For prospective buyers, Positron’s next test will be production hardware running their actual models. Useful comparisons will need to include response times, energy use, software compatibility and the full cost of operating the system.

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